Advantest (6857) Investor Update summary

Business environment and industry trends

• Semiconductors are integral to diverse applications, with AI and HPC driving demand for higher processing power and efficiency.

• Rapid advancements in packaging, integration, and miniaturization, such as HPC, HBM, and 3D/2.5D/3.5D integration, are reshaping the industry.

• The industry faces interconnected challenges: scaling, power, memory, I/O, device complexity, and energy efficiency.

• Increasing device complexity and integration in HPC/AI, automotive, RF, and power devices is driving demand for advanced SoC testers.

Technological and testing challenges

• Increasing device complexity and miniaturization require more advanced and integrated test solutions, raising test intensity.

• Test volumes for HPC/AI devices are rising due to more transistors, multi-die integration, and new process technologies.

• Heat management and quality assurance are critical as devices become more powerful and densely packed.

• Testing must address multiple processor and IO dies, high-bandwidth memory, and rapid data transfer requirements.

• Efficient, high-coverage testing is needed to manage increased test patterns and ensure quality in a short time frame.

Evolution of test processes and scan test

• Scan test volume has surged in the 2020s, outpacing other test types due to exponential transistor growth and enhanced functionality.

• Pattern generation efficiency has plateaued, making longer test times inevitable despite ongoing R&D.

• Additional test processes, such as die-level, mission mode, stress, and system-level tests, are being adopted for reliability and quality assurance.

• Built-in self-test (BIST) and DC tests have grown with increasing pin counts and device features.